1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, to storage capacitors for use in semiconductor memory devices.
2. Discussion of the Related Art
Capacitors comprising silicon dioxide (SiO.sub.2) are typically used in conventional dynamic random access memories (DRAMs). To achieve greater charge storage density for increasingly dense, next generation very large scale integrated circuits (VLSI), the SiO.sub.2 capacitors must likewise decrease in size. Silicon dioxide capacitors have a limited charge storage density, however, and in order to achieve adequate charge storage within an acceptable cell size, complex processes are needed to fabricate trench or stacked capacitors. The complexity arises in part due to the large trench depths or stacked capacitor heights needed to provide adequate surface area for charge storage. Thus, for the one-transistor memory cell concept to be viable for use in next generation 64- and 256-Mbit DRAMs, high dielectric constant (.epsilon..sub.r) materials may be needed. Use of such high dielectric constant materials will more easily allow a greater charge density in the storage capacitor, reduce the trench depth or capacitor height, and thereby simplify the capacitor fabrication process.
Examples of high dielectric constant (.epsilon..sub.r) materials for potential use in future DRAMs include insulators such as tantalum oxide (Ta.sub.2 O.sub.5), strontium titanium oxide (SrTiO.sub.3), and barium titanium oxide (BaTiO.sub.3). In order to achieve the stoichiometry and density required for a high dielectric constant with these insulators, the insulators must be annealed at high temperatures (typically, greater than 800 .degree. C.) in oxygen after deposition of the same. As a result of the high temperature anneal in an oxygen ambient and subsequent processing, underlying electrode materials, such as polysilicon, can also be oxidized. Oxidation of the underlying electrode materials degrades the performance of the resultant capacitor structure, thereby lowering the capacitance thereof.
In the article, "A STACKED CAPACITOR WITH (Ba.sub.x Sr.sub.1-x)TiO.sub.3 FOR 256M DRAM" by K. Koyama et al., IEDM Tech. Dig., 1991, pp. 823-826, a method of forming a stacked capacitor is disclosed in which platinum (Pt) is used as an electrode material for its oxidation resistance during RF-magnetron sputter deposition of the dielectric layer (Ba.sub.0.5 Sr.sub.0.5)TiO.sub.3. In addition, a tantalum (Ta) film is placed under the Pt layer to prevent silicon (Si) diffusion into the Pt at a contact area. Thus, a Pt/Ta double layer is required in the formation of the stacked capacitor as taught by K. Koyama et al. A disadvantage of the Pt/Ta double layer electrode is that the layers of the stacked capacitor of K. Koyama et al. are deposited and formed by sputter deposition, however, sputter deposition is not well suited for conformal sidewall coverage. While the use of high dielectric material reduces depth and height of a capacitor structure, adequate sidewall coverage is still required to ensure that a maximum capacitance is obtained. In another article, "CONDUCTING OXIDE ELECTRODES FOR FERROELECTRIC FILMS" by Kwok et al., ISIF Proc. 92, pp. 412-425, a method of forming a lead zirconate titanate (PZT) capacitor for non-volatile memories is disclosed and in which reactively sputtered ruthenium oxide (RuO.sub.2) is used as an electrode material. While RuO.sub.2 is used for its oxidation resistance during thermal annealing of the PZT material, the reactively sputtered RuO.sub.2 is not well suited for conformal sidewall coverage.
There is thus needed a capacitor, such as a stacked capacitor or other capacitor structure, and a simplified method of forming the same, the capacitor having a high dielectric constant and further having greater charge storage density. Such a capacitor, and method of making the same, should be well suited for providing a desired high charge storage capacity and further having an acceptable cell size for use in DRAMs.